Prediction of deformation during manufacturing processes of silicon interposer package with TSVs

نویسندگان

  • Yeonsung Kim
  • Ah-Young Park
  • Chin-Li Kao
  • Michael Su
  • Bryan Black
  • Seungbae Park
چکیده

Article history: Received 25 April 2016 Received in revised form 26 June 2016 Accepted 29 July 2016 Available online 10 August 2016 The purpose of this paper is to analyze and predict the thermal deformation of the through silicon via (TSV) interposer package during themanufacturing process and to perform a parametric study to minimize thewarpage and thermal stress. Samples were selected during different stages of the assembly to observe the thermal behavior change. TheDigital Image Correlation (DIC) techniquewas employed tomeasure the real-timedeformation of the samples under thermal loading. To make a finite element analysis (FEA) model, material properties were characterized by DIC and Dynamic Mechanical Analysis (DMA). Based on the material properties and deformation data determined by experiments, a validated FEAmodelwas established. To reduce themodeling complexity and the computing time in the simulation, the C4/underfill layer, micro bump/underfill layer, and TSV interposer were assumed to be isotropic. The most effective material properties for the isotropic layers were calculated by the composite theory. Also, the simulation followed the sequential manufacturing processes to investigate the thermal deformation change of each step and to obtain a more accurate prediction result. The thermal behavior from simulation showed a good agreement with the experimental result and this verified simulation model was implemented for the parametric study. A series of simulations were carried out to minimize the package warpage. To avoid any delamination failures, the stresses at the interface between the interposer and underfill were also evaluated. The effect of the interposer underfill material property, substrate material property, substrate thickness, and TSV density (Cu volume fraction) in the interposerwere studied. It has been shown that lowmodulus, low coefficient of thermal expansion (CTE), and high glass transition temperature (Tg) underfill, as well as a low modulus and low CTE substrate can mitigate the package warpage and stress development at the interface between interposer and underfill. Also, a larger Cu volume TSV interposer and thick substrate can lessen the warpage of the package and stress at the interface. © 2016 Elsevier Ltd. All rights reserved.

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عنوان ژورنال:
  • Microelectronics Reliability

دوره 65  شماره 

صفحات  -

تاریخ انتشار 2016